1. The instructions that pass through the fetch, decode and execution stages sequentially is known as
a) sequential instruction
b) sequence of fetch, decode and execution
c) linear instruction sequencing
d) non-linear instruction sequencing
2. During the execution of instructions, if an instruction is executed, then next instruction is executed only when the data is read by
a) control unit
b) bus interface unit
c) execution unit
d) CPU
3. Because of Pentium’s superscalar architecture, the number of instructions that are executed per clock cycle is
a) 1
b) 2
c) 3
d) 4
4. The type of execution which means that the CPU should speculate which of the next instructions can be executed earlier is
a) speculative execution
b) out of turn execution
c) dual independent bus
d) multiple branch prediction
5. The execution in which the consecutive instruction execution in a sequential flow is hampered is
a) speculative execution
b) out of turn execution
c) dual independent bus
d) multiple branch prediction
6. A dual independent bus has
a) enhanced system bandwidth
b) CPU that can access both cache and memory simultaneously
c) high throughput
d) all of the mentioned
7. The unit that is used to implement the multiple branch prediction in Pentium-Pro is
a) control unit
b) bus interface unit
c) branch target buffer
d) branch instruction register
8. Which of the following is not an independent engine of Pentium-Pro?
a) fetch-decode unit
b) dispatch-execute unit
c) control-execute unit
d) retire unit
9. The unit that accepts the sequence of instructions from the instruction cache as input is
a) fetch-decode unit
b) dispatch-execute unit
c) retire unit
d) none
10. In fetch-decode unit, the number of parallel decoders that accept the stream of fetched instructions and decode them is
a) 1
b) 2
c) 3
d) 4
a) sequential instruction
b) sequence of fetch, decode and execution
c) linear instruction sequencing
d) non-linear instruction sequencing
2. During the execution of instructions, if an instruction is executed, then next instruction is executed only when the data is read by
a) control unit
b) bus interface unit
c) execution unit
d) CPU
3. Because of Pentium’s superscalar architecture, the number of instructions that are executed per clock cycle is
a) 1
b) 2
c) 3
d) 4
4. The type of execution which means that the CPU should speculate which of the next instructions can be executed earlier is
a) speculative execution
b) out of turn execution
c) dual independent bus
d) multiple branch prediction
5. The execution in which the consecutive instruction execution in a sequential flow is hampered is
a) speculative execution
b) out of turn execution
c) dual independent bus
d) multiple branch prediction
6. A dual independent bus has
a) enhanced system bandwidth
b) CPU that can access both cache and memory simultaneously
c) high throughput
d) all of the mentioned
7. The unit that is used to implement the multiple branch prediction in Pentium-Pro is
a) control unit
b) bus interface unit
c) branch target buffer
d) branch instruction register
8. Which of the following is not an independent engine of Pentium-Pro?
a) fetch-decode unit
b) dispatch-execute unit
c) control-execute unit
d) retire unit
9. The unit that accepts the sequence of instructions from the instruction cache as input is
a) fetch-decode unit
b) dispatch-execute unit
c) retire unit
d) none
10. In fetch-decode unit, the number of parallel decoders that accept the stream of fetched instructions and decode them is
a) 1
b) 2
c) 3
d) 4